指導教授
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陳永源教授
Yung-Yuan Chen

(O): 02-8674-1111 ext. 66014
E-mail: chenyy@mail.ntpu.edu.tw
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最高學歷
國立交通大學計算機工程學系 學士
美國紐約州立大學水牛城分校計算機科學系 碩士
美國紐約州立大學水牛城分校電機與計算機工程學系 博士
專長
容錯系統設計與分析,系統晶片設計及強韌度分析,車用電子系統設計與開發,線傳駕駛控制系統設計與驗證, 可靠度工程,系統機制安全設計與驗證
經歷
中央研究院資訊所助理
紐約州立大學水牛城分校電腦中心顧問
約州立大學水牛城分校電機與計算機工程系助教
紐約州立大學水牛城分校電機與計算機工程系研究助理
中華大學資訊工程學系 副教授/教授
中華大學資訊工程學系 系主任
華大學資訊管理學系 系主任
國立交通大學電機與控制工程學系 兼任副教授
Aplus Flash Technology Corp., San Jose, U.S.A Senior Design Engineer
教授過的課程
大學部: 電子電路學 (包含電路板及Spice模擬實驗)、邏輯電路、 數位系統、 微處理機系統、 計算機結構、超大型積體電路簡介、超大型積體電路設計與應用、嵌入式硬體平台設計
研究所: 進階超大型積體電路設計、超大型積體電路測試、嵌入式系統、容錯計算、超大型積體電路專題、車用通訊網路控制系統、智慧電子應用設計概論
最近五年研究興趣
容錯處理器及系統設計
注入錯誤技術開發
系統晶片設計與可靠度驗證分析
嵌入式系統設計與可靠度驗證方法、流程及分析平台的研發
線傳駕駛系統設計、驗證分析與測試
● FlexRay 控制網路通訊可靠度研究
1. FlexRay通訊協定容錯機制探討、容錯設計及其應用策略的探討以及可靠度測試驗證與分析平台的開發建立
2. 線傳轉向控制系統安全設計個案研究
系統可靠度工程
系統機制安全設計與驗證
研究成果
提出一個有效的容錯處理器架構及容錯技術驗證分析流程和工具平台;此研究最主要的貢獻在於有效提升處理器控制流程和資料路徑的可靠度以及即時偵查錯誤和克服的能力。
VHDLSystemC系統設計層級提出一個可行的錯誤注入方法和工具;目前在SystemC系統設計層級上錯誤注入的研究,尚屬一個相當新的研究議題,所發表的研究論文數量不多。在這領域已有一些不錯的成果,並且在最近幾年的國際會議上發表數篇研究結果,論文已陸續在幾個典型的IEEE相關領域的會議所發表的論文中被引用。
SystemC系統層級建立系統晶片之可靠度測試驗證與分析平台,包含軟體實踐錯誤注入與模擬實踐錯誤注入的方法及工具,以及FMEA的分析模型和工具,來幫助設計者可以快速的掌握到系統設計上的脆弱點和可靠度的問題點,以及元件失敗對系統可靠度影響的等級分類,進而提出有效的改善對策來解決可靠度/安全度的問題。這個研究相當有價值與實用,所提出的可靠度測試驗證與分析技術,在SystemC CoWare Platform Architect環境上建立出一個工具平台,並用一個實際的ARM-based系統晶片來展示驗證分析工具的可行性,以及系統晶片強韌度和FMEA分析結果的討論。
● FlexRay 控制網路通訊可靠度研究 (包含FlexRay通訊協定容錯機制探討、容錯設計及其應用策略的探討以及可靠度測試驗證與分析平台的開發建立)。這個課題在學術界和產業界,都是一項極為新穎與重要的研究。積極的在推動FlexRay 控制網路的發展與應用,也是團隊研究計畫重要的規劃與執行者。
線傳轉向控制系統安全設計個案研究
● ISO 26262機制安全設計與驗證
五年協助產業發展績效:
l Porting MicroC/OS-II to SocleTM LDK 3.1 ARM-based platform: 協助虹晶科技股份有限公司將MicroC/OS-II 移植到該公司所開發的,以ARM為核心的系統平台上
l 虹晶科技股份有限公司共同執行(96)科學工業園區人才培育補助計畫: 嵌入式系統設計與應用開發人員培育模組課程(含企業實習)中之嵌入式硬體平台設計課程,以及共同指導學生至企業實習
l 財團法人車輛研究測試中心顧問,九十七年十二月一日至九十八年五月三十日。內容: FlexRay通訊可靠度研究
l ARTC車輛網路技術座談會講師,講題: FlexRay通訊可靠度研究,2009519
l 普家康興業股份有限公司贊助本團隊兩塊FlexRay Node實驗板,價值20萬元,讓本團隊的實驗室在FlexRay線傳駕駛系統設計、驗證及安全性的研究環境更為完善20103
l 參加由財團法人車輛研究測試中心(ARTC) ,於台大集思會議中心所舉辦的 “高安全控制網路通訊技術研討會”暨 學計畫「高安全控制網路平台技術」之成果發表會,並且擔當其中一個場次的引言人,議題:車載網路通訊驗證技術分析,2010429日。
l 財團法人車輛研究測試中心(ARTC) 所舉辦的先進底盤系統開發與趨勢研討會: “ISO26262車用電子安全性設計介紹”場次的共同主講人 20101130
l 目前我們團隊正在與SGS台灣分公司、金屬工業研究發展中心及相關業界,籌組"車用電子安全性暨可靠性前瞻技術聯盟"SGS台灣分公司希望借重我們團隊在此領域累積的技術、經驗和研發成果,希望透過聯盟來推動車用電子安全性暨可靠性前瞻技術,協助產業界技術和研發能力的升級。此聯盟主要是要推動ISO 26262 的汽車電子系統安全度設計測試和驗證標準,希望能建立一套符合ISO 26262安全規範的設計驗證流程,並以safety case來驗證流程的可行性及正確性。希望將此符合ISO 26262安全規範的設計驗證流程引進到產業界,協助高階車用電子的產品可以符合ISO 26262安全規範。
五年國內外之成就與榮譽:
l Program committee: Symposium on Risk Management and Cyber-Informatics: RMCI '2004-2011, Florida USA.
l Yung-Yuan Chen, Cheng-Ming Tsai, Hsueh-Chung Liu & Hung-Chuan Lai, “The Comprehensive Fault-Tolerant Schemes for VLIW Processor”, 7th World Multi-Conference on Systemics, Cybernetics and Informatics (Best Paper Award in the session: Computer Science and Engineering), Florida USA, pp. 71-76, July 2003. NSC 89-2218-E-216-010 and NSC 90-2213-E-216-021
l Yung-Yuan Chen, Kuen-Long Leu and Kun-Chun Chang, “Datapath Error Detection with Hybrid Detection Approach for High-Performance Microprocessors,” 12th WSEAS International Conference on Computers, pp. 95-100, July 2008. (Best Paper Award) NSC 96-2221-E-216-006
l Invited paper for 3rd WSEAS International Conference on CIRCUITS, SYSTEMS, SIGNAL & TELECOMMUNICATIONS, January 2009, China.
l Invited to participate in the 60th meeting of IFIP Working Group 10.4 on Dependable Computing and Fault Tolerance, July 1-4, 2011. This meeting is by invitation only for people in dependable and secure computing community from all over the world to attend. About 10 from Taiwan are invited.
l Keynote Speaker: The 2011 International Conference on Computer Engineering and Applications (ICCEA 2011), Haikou, China, July 15 – 17, 2011.
l Invited to contribute to the forthcoming Open Access book, "Embedded System" (ISBN 979-953-307-580-7), which will be published by InTech, Open Access publisher of books and journals in the fields of science, technology and medicine. Publication of the book is scheduled for 26 January, 2012.
l Invited reviewer of Journal of Systemics, Cybernetics and Informatics
l Reviewer of IEEE Trans. on Computers, IEEE Trans. on VLSI Systems, IEEE Trans. on Reliability, Journal of Information Science and Engineering, Journal of Supercomputing, Journal of Circuits, Systems and Computers, Chinese Journal of Aeronautics (SCIE, EI), IEEE International Conference on VLSI Design, IEEE International Conference on Dependable Systems and Networks, Symposium on Risk Management and Cyber-Informatics, World Multi-Conference on Systemics, Cybernetics and Informatics etc..
五年在人才培育、研究團隊建立及服務方面的重要貢獻及成就:
l 建立FlexRay智慧型控制網路系統可靠度/安全度研究團隊: 我們的研究團隊參與 ‘高安全控制網路通訊平台技術研發’的研究計畫,與國立中央大學電機工程學系、國立中山大學電機工程學系和財團法人車輛研究測試中心等單位,共同合作研發高安全控制網路通訊平台技術。
l 帶領兩位博士班研究生到奧地利維也納,與FlexRay技術著稱的TTTechTM 公司做技術交流,並討論可能的合作機會。目前已安排一位博士生到德國University of Erlangen-Nuremberg Prof. Teich的研究團隊,做一年的技術研習交流和研究合作
l 指導學生參加 智慧電子應用設計聯盟所舉辦之「2012智慧電子創新應用與設計競賽」車用電子創意組,獲得佳作。
究成果目錄:論文及著述
A. Journal Paper
1. Yung-Yuan Chen & Shambhu J. Upadhyaya, June 1993, "Reliability, Reconfiguration and Spare Allocation Issues in Binary Tree Architecture Based on Multiple-Level Redundancy, IEEE Trans. on Computers, VOL. 42, No.6, pp.713-723. (SCI)
2. Yung-Yuan Chen & Shambhu J. Upadhyaya, Sept. 1993, “Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy,” IEEE Trans. on Computers, VOL. 42, No.9, pp.1136-1141. (SCI)
3. Yung-Yuan Chen & Shambhu J. Upadhyaya, June 1994, "Modeling the Reliability of a Class of Fault Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy," IEEE Trans. on Computers, VOL. 43, No.6, pp.737-748. (SCI)
4. Yung-Yuan Chen, Ching-Hwa Cheng and Yung-Ci Chou, Oct. 1994, “An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors”, First European Conference on Dependable Computing (EDCC-1), pp.421-438, Berlin, Germany. (Springer-Verlag: Lecture Notes in Computer Science 852) (SCI)
5. Gene Eu Jan, Ming-Bo Lin & Yung-Yuan Chen, June 1997, "Computerized Shortest Path Searching for Vessels," Journal of Marine Science and Technology, VOL.5, No.1, pp. 95-99.
6. Yung-Yuan Chen, Shambhu J. Upadhyaya & Ching-Hwa Cheng, Dec.1997, "A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors," IEEE Trans. on Computers, Vol.46, No. 12, pp.1363-1371. (SCI)
NSC 82-0404-E-216-035 and NSC 83-0404-E-216-002
7. Yung-Yuan Chen, "Concurrent Detection of Processor Control Errors by Hybrid Signature Monitoring," Third European Dependable Computing Conference held in Prague, Czech Republic, pp. 437-454, September 1999. (Springer: Lecture Notes in Computer Science 1667) (SCI)
8. 陳永源 利用看守狗處理器在同步錯上之研究 第四十二期國科會工程科技通訊 pp. 38-39, Dec. 1999
9. Yung-Yuan Chen and Gene Eu Jan, “Resource Placement in Star Network,” Chung Hua Journal of Science and Engineering, Vol. 1, No. 2, pp.61-70, Sept. 2003.
10. Yung-Yuan Chen and Hung-Chuan Lai, “A Comprehensive Study of Fault-Tolerant VLIW Processors,” Chung Hua Journal of Science and Engineering, Vol. 2, No. 2, pp.49-54, June 2004.
11. Yung-Yuan Chen, “Embedding Watchdog Processor Scheme in VLIW Architecture,” Chung Hua Journal of Science and Engineering, Vol. 3, No. 1, pp. 153-159, Jan. 2005. (NSC 93-2213-E-216-019)
12. Yung-Yuan Chen and Kuen-Long Leu, “Signature-monitoring technique based on instruction-bit grouping,” IEE Proceedings- Computers and Digital Techniques, Vol. 152, No. 4, pp. 527-536, July 2005. (SCI, EI)
13. Yung-Yuan Chen, “Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring,” IEEE Trans. on Computers, Vol. 54, No. 10, pp. 1298-1313, October 2005. (SCI) (NSC 87-2213-E-216-001)
14. Yung-Yuan Chen, “Incorporating Fault-Tolerant Features in VLIW Processors”, International Journal of Reliability, Quality and Safety Engineering, Vol. 12, No. 5, pp. 397-411, October 2005. (EI) (NSC 89-2218-E-216-010 and NSC 90-2213-E-216-021)
15. Yung-Yuan Chen, “A Fault Diagnosis Scheme and Its Quality Issue in Reconfigurable Array Architecture,” Journal of Computer Science and Technology, Vol. 6, No. 1, pp. 12-21, April 2006.
16. Yung-Yuan Chen, Kuen-Long Leu and Chao-Sung Yeh, “Fault-Tolerant VLIW Processor Design and Error Coverage Analysis,” The 2006 IFIP International Conference on Embedded And Ubiquitous Computing, pp. 754-765, August 2006. (Springer: Lecture Notes in Computer Science 4096) (SCI) (NSC 92-2213-E-216-005 and NSC 93-2213-E-216-019)
17. Yung-Yuan Chen, Kuen-Long Leu and Kun-Chun Chang, “Datapath Error Detection with Hybrid Detection Approach for High-Performance Microprocessors,” WSEAS Transactions on Computers, Vol. 7, Issue 8, pp. 1337-1351, August 2008. (EI) (NSC 96-2221-E-216-006)
18. Yung-Yuan Chen, Chung-Hsien Hsu, and Kuen-Long Leu, “Analysis of System Bus Transaction Vulnerability based on FMEA Methodology in SystemC TLM Design Platform,” WSEAS Transactions on Computers, Issue 2, Vol. 8, pp. 406-416, Feb. 2009. (EI) (NSC 97-2221-E-216-018)
19. Yung-Yuan Chen and Kuen-Long Leu, “Reliable Data Path Design of VLIW Processor Cores with Comprehensive Error-Coverage Assessment,” Microprocessors and Microsystems, Vol. 34, Issue 1, pp. 49-61, Feb. 2010. (SCI) (NSC 96-2221-E-216-006 and NSC 97-2221-E-216-018)
20. Yung-Yuan Chen and Gene Eu Jan, “Development of Scenario-Based Fault Injection Platform and Its Application Study,” Tamkang Journal of Science and Engineering, Vol. 13, No. 2, pp. 205-214, June 2010. (EI)
21. Shi-Jinn Horng, Hung-Chuan Lai, Minyi Guo, Yung-Yuan Chen, “A Run Time Error Checking for VLIW Processors,” submitted to IEEE Transactions on Parallel and Distributed Systems, June 2011. (SCI)
22. Yung-Yuan Chen, “Development of SoC-level safety process in SystemC design platform for safety-critical systems,” submitted to Microprocessors and Microsystems, August 2011. (SCI) (NSC 97-2221-E-216-018 and NSC 98-2221-E-305-010)
23. Yung-Yuan Chen, Che-Hao Chang and Gene Eu Jan, “Study the Effect of Delayed Frame Errors on FlexRay Communication Systems,” accepted to be published at Advanced Science Letters, August 2011. (SCIE) (NSC 99-2221-E-305-016)
24. Yung-Yuan Chen, Shie-Lung Li, and Gene Eu Jan, “Development of Fault Scenario Generator Tool for FlexRay Communication Systems,” Energy Procedia (ELSEVIER), Vol. 13, pp. 8938-8945, 2011. (EI) (NSC 99-2221-E-305-016)
25. Yung-Yuan Chen and Tong-Ying Juang, “Vulnerability Analysis and Risk Assessment for SoCs used in Safety-Critical Embedded Systems,” a book chapter in “Embedded Systems - theory and design Methodology”, ISBN 978-953-51-0167-3, edited by Kiyofumi Tanaka, published by InTech - Open Access publisher of books and journals in the fields of science, technology and medicine, pp. 51-72, March 2012.
26. Gene Eu Jan, Cheng-Hong Li, Yung-Yuan Chen, and Shan-Hui Ho, “A Novel Approach to the Seat Assignment Problem,” accepted to be published at Sensor Letters, 2011. (SCIE)
B. Best Paper Award and EI Conferences
1. Yung-Yuan Chen, Cheng-Ming Tsai, Hsueh-Chung Liu & Hung-Chuan Lai, “The Comprehensive Fault-Tolerant Schemes for VLIW Processor”, 7th World Multi-Conference on Systemics, Cybernetics and Informatics (Best Paper Award in the session: Computer Science and Engineering), Florida USA, pp. 71-76, July 2003.
NSC 89-2218-E-216-010 and NSC 90-2213-E-216-021
2. Yung-Yuan Chen and Kun-Feng Chen, “Incorporating Signature-Monitoring Technique in VLIW Processors,” 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 395-402, Cannes France, Oct. 2004. (EI) NSC 93-2213-E-216-019
3. Yung-Yuan Chen, Kuen-Long Leu and Li-Wen Lin, “Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors,” The 2006 International Conference on Computer Design, pp. 196-202, Las Vegas, USA, June 2006. (EI) NSC 92-2213-E-216-005 and NSC 93-2213-E-216-019
4. Kuen-Long Leu, Yung-Yuan Chen and Jwu-E Chen, “A Comparison of Fault Injection Experiments under Different Verification Environments”, IEEE Fourth International Conference on Information Technology & Applications, pp. 582-587, Jan. 2007. (EI) NSC 95-2221-E-216-015
5. Yung-Yuan Chen and Geng-Wei Wu, “Fault-Tolerant Verification Platform for Systems Modeled at High Level of Abstraction”, 1st IEEE Systems conference, pp. 1-7, April 2007. (EI) NSC 95-2221-E-216-015
6. Hung-Chuan Lai, Shi-Jinn Horng, Yung-Yuan Chen, Pingzhi Fan, and Yi Pan, “A New Concurrent Detection of Control Flow Errors Based on DCT Technique,” 13th IEEE Pacific Rim International Symposium on Dependable Computing, pp. 201-209, Dec. 2007. (SCI, EI)
7. Yung-Yuan Chen, Kuen-Long Leu and Kun-Chun Chang, “Datapath Error Detection with Hybrid Detection Approach for High-Performance Microprocessors,” 12th WSEAS International Conference on Computers, pp. 95-100, July 2008. (EI) NSC 96-2221-E-216-006.
8. Kun-Chun Chang, Yi-Chinag Wang, Chung-Hsien Hsu, Kuen-Long Leu and Yung-Yuan Chen, “System-Bus Fault Injection in SystemC Design Platform,” 2nd IEEE International Conference on Secure System Integration and Reliability Improvement, pp. 211-212, July 2008. (EI) NSC 95-2221-E-216-015, NSC 96-2221-E-216-006.
9. Yung-Yuan Chen, Shu-Hao Hsu, and Kuen-Long Leu, “An Estimation Model of Vulnerability for Embedded Microprocessors,” 2nd IEEE International Conference on Secure System Integration and Reliability Improvement, pp. 224-225, July 2008. (EI) NSC 96-2221-E-216-006.
10. Yung-Yuan Chen, Yi-Chiang Wang, and Jian-Min Peng, “SoC-Level Fault Injection Methodology in SystemC Design Platform,” Asia Simulation Conference 2008/ the 7th International Conference on System Simulation and Scientific Computing, pp. 680-687, October 2008. (EI) NSC 97-2221-E-216-018
11. Hung-Chuan Lai, Shi-Jinn Horng, and Yung-Yuan Chen, “An Online Control Flow Check for VLIW Processor,” 14th IEEE Pacific Rim International Symposium on Dependable Computing, pp. 256-264, Dec. 2008. (EI)
12. Yung-Yuan Chen, Chung-Hsien Hsu, and Kuen-Long Leu, “Analysis of System Bus Transaction Vulnerability in SystemC TLM Design Platform,” 3rd WSEAS International Conference on Computer Engineering and Applications, pp. 284-289, January 2009, China. (EI) NSC 97-2221-E-216-018
13. Yung-Yuan Chen, Chung-Hsien Hsu, and Kuen-Long Leu, “SoC-Level Risk Assessment Using FMEA Approach in System Design with SystemC,” IEEE Symposium on Industrial Embedded Systems, pp. 82-89, July 2009, Switzerland. (EI) NSC 97-2221-E-216-018
14. Kuen-Long Leu, Yung-Yuan Chen, Chin-Long Wey and Jwu-E Chen, “Robustness Investigation of the FlexRay System,” IEEE Symposium on Industrial Embedded Systems, pp. 148-151, July 2009, Switzerland. (EI)
15. Gene Eu Jan, Ming Che Lee, S. G. Hsieh, Yung-Yuan Chen, “Transportation Network Navigation with Turn Penalties,” IEEE/ASME International Conference on Advanced Intelligent Mechatronics, pp. 1224-1229, July 2009. (EI)
16. Kuen-Long Leu, Yung-Yuan Chen, Chin-Long Wey, Jwu-E Chen and Chung-Hsien Hsu, “A Bayesian Network Reliability Modeling for FlexRay Systems,” International Conference on Information and Communication Technologies, pp. 406-411, May 2010.
17. Kuen-Long Leu, Yung-Yuan Chen, Chin-Long Wey, Jwu-E Chen, “A verification flow for FlexRay communication robustness compliant with IEC 61508,” The 2nd International Conference on Industrial Mechatronics and Automation, pp. 228-231, May 2010.
18. Kuen-Long Leu, Yung-Yuan Chen, Chin-Long Wey, Jwu-E Chen, “Robustness Analysis of the FlexRay System through Fault Tree Analysis,” 2010 IEEE International Conference on Vehicular Electronic and Safety, pp. 30-35, July 2010.
19. Shie-Lung Li, Yung-Yuan Chen, Jen-Chieh Fang, Jin-Tai Yan, “Development and Application of Fault Injection Platform in FlexRay Drive-by-Wire Systems,” International Conference on Future Industrial Engineering and Application (ICFIEA), pp. 394-397, December 2010.
20. Yung-Yuan Chen, Shie-Lung Li, and Gene Eu Jan, “Development of Fault Scenario Generator Tool for FlexRay Communication Systems,” 2011 3rd International Conference on Computer Engineering and Applications, pp. V1-409 to V1-413, July 2011.
C. Conference Paper
  • 1. Yung-Yuan Chen & Shambhu J. Upadhyaya, June 1990," An Analysis of a Reconfigurable Binary Tree Architecture Based on Multiple-Level Redundancy," 20th Annual IEEE Int. Symp. on Fault Tolerant Computing, pp.192-199
  • 2. Shambhu J. Upadhyay & Yung-Yuan Chen, Jan. 1991,"Yield and Layout Issues in Fault Tolerant VLSI Architectures," VLSI Design'91:4th IEEE in Int. Symp. pp.255-260
  • 3. Yung-Yuan Chen & Shambhu J. Upadhaya, Nov.1991,"A New Approach to Modeling the Performance of a Class of Fault Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy," IEEE Int. Workshop on Defect and Fault Tolerance on VLSI System, pp.157-160
  • 4. Yung-Yuan Chen, Yung-Shiuan Shyu and Ching-Hwa Cheng, Aug 1993, "An Effective Framework for Fault-Tolerant VLSI/WSI Arrays Based on Hybrid Redundancy Approach," 1993 4th Workshop on VLSI DESIGN/CAD, pp.231-235.
  • 5. Mill-Jer Wang, Jwe-E Chen and Yung-Yuan Chen, Sep. 1993, "A New Test Plan and The Effect of Error Testing on Quality Level Prediction", 1993 5th International Symposium on IC Technology, System and Applications, SINGAPORE, pp.343-347.
  • 6. Yung-Yuan Chen, Yung-Shiuan Shyu and Ching-Hwa Cheng, Jan. 1994, "An Effective Framework for Fault-Tolerant VLSI/WSI Arrays Based on Hybrid Redundancy Approach", IEEE International Conference on Wafer-Scale Integration, pp.153-162
  • 7. Yen-Shung Chang, Jwu E Chen and Yung-Yuan Chen, Aug. 1994, "Error Classification by Wafer Map Analysis", The Fifth VLSI Design/CAD Symp. pp. 211-214, Taiwan, R.O.C.
  • 8. Yung-Yuan Chen, Ching-Hwa Cheng and Yung-Ci Chou, Aug. 1994, "The Design and Analysis of Fault-Tolerant VLSI/WSI Array Processors", IEEE Region 10's Ninth Annual International Conference on: "Frontiers of Computer Technology", pp.637-641, Singapore.
  • 9. Mill-Jer Wang, Jwu-E Chen and Yung-Yuan Chen, Nov. 1994. "To Verify Manufacturing Yield by Testing", IEEE Third Asian Test Symposium, pp.385-390, Nara, Japan.
  • 10. Yung-Yuan Chen, Sau-Gee Chen and Jiann-Cherng Lee, Jan. 1995, "Yield and Performance Issues in Fault-Tolerant WSI Array Architectures", IEEE International Conference on Wafer-Scale Integration, San Francisco, U.S.A.
  • 11. Yung-Yuan Chen, Ching-Hwa Cheng and Jwu-E Chen, Jan. 1995, "An Efficient Switching Network Fault Diagnosis for Reconfigurable VLSI/WSI Array Processors", IEEE Eighth International Conference on VLSI Design, pp. 349-354, New Delhi, India.
  • 12. Mill-Jer Wang, Jwu E Chen and Yung-Yuan Chen, Aug.1995,"Intergrating Test Economics into IC Development Processor",1995 6th VLSI Design/CAD Symposium,pp.69-72.
  • 13. Mill-Jer Wang,Yen-Shung Chang, Jwu E Chen, Yung-Yuan Chen and Shaw Cherng Shyu, Nov.1996,"Yeild Improvement by Test Error Cancellation", Fifth Asian Test Symposium,pp.258-262.
  • 14. Gene Eu Jan, Ming-Bo Lin and Yung-Yuan Chen, May 1997,"A Novel Design of Super Concentrator-Base Load Balancer for Highly Parallel Computers",1997 Workshop on Distributed System Technologies & Applications,pp.589-596
  • 15. Yung-Yuan Chen and Chungti Liang, May 1997,"Resource Placement in Star Network",1997 Workshop on Distributed System Technologies & Applications,pp.479-488
  • 16. Jih-Jeen Chen, Yung-Yuan Chen, Chun-Yeh Liu, and A.W.Su, Aug. 1997,"The Architectural Design of a DSP Processor with Multimedia Instructions," The 8th VLSI Design/CAD Symposium,pp.313-316.
  • 17. Gene Eu Jan, Jin Yan Hsu and Yung-Yuan Chen, Nov. 1997 " Computerized shortest path searching and automatic collision-avoidance system," The 4th Transportation Safety Symposium, National Chung Kung Univ., Taiwan, pp. 153-162
  • 18. Yung-Yuan Chen, Chi-Jen Lee, Romg-Hao Lin and Chang-Lung Larn, "A Design and Testing of Pipeline DSP Processor with Special Application in H.263 Codec Processor," The 10th VLSI Design/CAD Symposium, pp. 149-152, August 1999.
  • 19. Yung-Yuan Chen, Leifone Chen & Chang-Lung Larn, "Fault Injection into VHDL Models: Fault Analysis of a Pipeline Processor," The 11th VLSI Design/CAD Symposium, pp. 231-234, August 2000.
  • 20. Gene Eu Jan, Lokar J. Y. Lin, W. R. Liou and Y. Y. Chen, "The Design and Implementation of a 2048-bit RSA Encryption/Decryption Chip," The 2003 International Conference on VLSI, Las Vegas, U. S. A., pp. 329-335, June 2003.
  • 21. Hung-Chuan Lai, Shi-Jinn Horng and Yung-Yuan Chen, "A Comprehensive Design Framework for Fault-Tolerant VLIW Processors," The 14th VLSI Design/CAD Symposium, pp. 301-304, August, 2003.

NSC 92-2213-E-216-005

22. Yung-Yuan Chen, Shi-Jinn Horng and Hung-Chuan Lai, "An Integrated Fault-Tolerant Design Framework for VLIW Processors," Proceedings of 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 555-562, Boston U.S.A., November 2003. NSC 92-2213-E-216-005

  • 23. Yung-Yuan Chen and Cheng-Chung Tai, "Power-Effective Fault-Tolerant VLIW Processors," 8th World Multi-Conference on Systemics, Cybernetics and Informatics, pp. 156-161, Florida USA, July 2004.

NSC 92-2213-E-216-005 and CHU-91-E-007

  • 24. Kun-Feng Chen and Yung-Yuan Chen, "VLIW Processor with Embedded Watchdog Processor for Control Flow Error Detection," The 15th VLSI Design/CAD Symposium, pp. August 2004.
  • 25. Yung-Yuan Chen and Kuen-Long Leu, "A New Signature-Monitoring Technique Based on Instruction Bit Grouping," The 15th VLSI Design/CAD Symposium, August 2004.
  • 26. Kun-Jun Chang and Yung-Yuan Chen, "System-Level Fault Injection in SystemC Design Platform," 8th International Symposium on Advanced Intelligent Systems, pp. 354-359, Sept. 2007. NSC 95-2221-E-216-015
  • 27. Meng-Ju Shih, Yung-Yuan Chen and Gene Eu Jan, "Experimental Assessment of Fault Coverage for Fault-Tolerant High-Performance Processors," 8th International Symposium on Advanced Intelligent Systems, pp. 564-569, Sept. 2007.
  • 28. 汪碩彥、陳永源, "利用軟體實踐錯誤注入進行嵌入式系統的強韌度驗證", 2008資訊系統應用學術研討會, October 2008.
  • 29. 陳信宇、陳永源, "系統晶片強韌度驗證分析工具平台開發",2009全國計算機會議,pp. 1-12, November 2009.
  • 30. Jen-Chieh Fang, Yung-Yuan Chen, Jin-Tai Yan, Gene Eu Jan, "Fault Injection Platform Compliant with EN50159 for FlexRay Drive-by-Wire Systems," 2010 Cross-Strait Conference on Information Science and Technology, pp. 179-183, July 2010.
D. 報告
1. Yung-Yuan Chen and Chun-Yeh Liu, Aug. 1997, 超大型積體電路設計導論與實驗計畫報告 八十六年度大學校院VLSI 教育改進計畫 教育部顧問室。
2. Yung-Yuan Chen, Aug. 1998, 進階超大型積體電路系統設計計畫報告 八十七年度大學校院VLSI 教育改進計畫教育部顧問室。
3. 陳永源,線傳行控系統前瞻控制網路技術研究與開發系統失效安全/網路容錯技術成果報告國防部軍備局中山科學研究院97年度委託學術合作研究計畫,九十七年九月。
4. 陳永源,FlexRay通訊可靠度研究成果報告,財團法人車輛研究測試中心委託合作案,九十八年六月。
5. 許仲賢,張坤鈞,陳永源,魏慶隆,使用FlexRay架構建立一個線傳控制系統Drive-by-Wire實驗平台經濟部技術處高安全控制網路通訊平台技術開發計畫-子計畫: 高可靠度的容錯通訊技術九十九年五月。
6. 呂昆龍,陳永源,魏慶隆,有效的高可靠度FlexRay通訊系統設計流程經濟部技術處高安全控制網路通訊平台技術開發計畫-子計畫: 高可靠度的容錯通訊技術九十九年五月。
最近更新在 週四, 26 四月 2012 18:43